The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, improvement in device drive current is becoming more important. When device dimensions are reduced to 130 nm and lower, particular 65 nm and lower, conventional methods for improving device drive current, such as shortening gate length and increasing gate capacitance, become difficult to implement. Further methods such as increasing carrier mobility have thus been explored.
Among efforts made to enhance carrier mobility, forming a stressed silicon channel is a known practice. Stress, sometimes referred to as strain, can enhance electron and hole mobility. The performance of a metal-oxide-semiconductor (MOS) device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon is placed under stress, the electron mobility is dramatically increased. Stress in a device may have components in three directions: parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The stress parallel to the device channel length and width are called in-plane strains. Research has revealed that a bi-axial, in-plane tensile stress field can improve NMOS performance, and compressive stress parallel to the channel length direction can improve PMOS device performance.
Stress can also be applied by forming a stressed capping layer, such as a stressed contact etch stop layer (CESL), on the MOS device. When a stressed CESL is deposited, the stress is imparted to the channel region. To achieve optimized performance, NMOS devices and PMOS devices preferably have a tensile-stressed CESL and a compressive-stressed CESL, respectively, although higher cost may be involved in forming stressed CESLs. FIG. 1 illustrates a cross-sectional view of this scheme. A PMOS device 2 has an overlying compressive-stressed CESL 6, and an NMOS device 4 has an overlying tensile-stressed CESL 8. The CESLs 6 and 8 are typically formed of silicon nitride (Si3N4) using different formation processes in order to generate different types of stresses.
PMOS devices formed using the conventional methods suffer reliability issues, however. The typical formation processes of Si3N4 generate hydrogen-containing by-products, which form bonds (Si—H) with silicon. These bonds may be broken later, generating interface traps at the interface of the gate oxide and silicon substrate, which causes a reliability issue called negative bias temperature instability (NBTI). NBTI results in a threshold voltage shift and a loss of drive current as a function of time. NBTI in PMOS devices has become one of the most critical reliability issues that ultimately determine the lifetime of integrated circuits.
Therefore, for future-generation integrated circuits, a fabrication method that solves the NBTI issue for PMOS devices is needed.